This invention relates to a semiconductor device, and in particular, to a MOSFET which is formed over a SOI (Silicon On Insulator) substrate.
Conventionally, a MOS transistor is often formed on an insulator as a thin-film semiconductor device by the use of the known SOI substrate.
Specifically, an oxide film (namely, an insulator) is embedded in a silicon substrate. Further, an active region (a silicon layer) is formed on the oxide film. In this event, a source diffusion layer, a drain diffusion layer and a channel region are formed in the active region, respectively. Moreover, a gate region is formed over the channel region via a gate oxide film. Herein, the gate region is formed by a polysilicon. In addition, side walls are formed at both side surfaces of the gate region.
In this case, the source and drain diffusion layers are formed by implanting or doping impurity ions after patterning the gate region and forming the side walls. Herein, the ion implantation is carried out by using the gate region and the side walls as a mask in the known self-alignment manner. Consequently, the channel length which determines the performance of the MOS transistor is determined by fine process accuracy of the gate region and the side walls.
In this event, the gate region is generally formed by the following processes.
(1) Growth of a gate electrode (polysilicon) PA1 (2) Application of a photoresist PA1 (3) Patterning of the photoresist PA1 (4) Etching of the gate electrode
The gate length is mainly determined by (3) the patterning of the photoresist and (4) the etching of the gate electrode.
Recently, the semiconductor device having the gate length of 0.35 .mu.m level is practically used. However, as the gate length is further shortened, it becomes difficult to keep the process accuracy in the conventional MOS transistor.
On the other hand, a CMOS circuit is often structured as an inverter by the MOS transistors (an N-channel MOS transistor and a P-channel MOS transistor). Further, a latch circuit is constituted by connecting a plurality of CMOS circuits. In this case, the diffusion layer in the active region is connected to the gate region by the use of a wiring layer. Consequently, the layout area of the circuit is increased to reduce integration degree of the device because the wiring layer is additionally required to connect between the diffusion layer and the gate region.